J-K FLIP-FLOPS WITH PRESET AND CLEAR.


SN5476, SN54LS76A, SN7476, SN74LS76A (DUAL J-K FLIP-FLOP)

The SN5476, SN54LS76A SN7476, SN74LS76A contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The SN5476, SN54LS76A SN7476, SN74LS76A is a positive-edge-triggered flip-flop. J-K inputs is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR.


The LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.

The SN5476 and the SN54LS76A are characterized for operation over the full military temperature range of -55C to 125C. The SN7476 and the SN74LS76A are characterized for operation from 0C to 70C   

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.

SN5476 , SN7476

  • Logic diagram (positive logic)
Logic diagram (positive logic)


  • Logic symbols
Logic symbols


  • Schematic of inputs and outputs
Schematic of inputs and outputs


SN54LS76A , SN74LS76A

  • Logic diagram (positive logic)
Logic diagram (positive logic)


  • Logic symbols
Logic symbols


  • Schematic of inputs and outputs
Schematic of inputs and outputs


Post a Comment

0 Comments